商品描述： Chip multiprocessors have been the mainstream in computer architecture. Such processors have more than one core on a single chip to obtain higher performance and lower power consumption. However， when more and more cores are integated onto the chip， the increasing number of cores makes the communication become the center of the on-chip architecture. It has become a new challenge on how to utilize these integrated cores in a single area with high efficiency. This book provides the explorative research on the above problems. There are four main topics discussed in this book. The first is the hybrid on-chip structure， which consists of the on-chip network and the on-chip bus. The bus is used to connect the local neighbours， and the network is used to connect the remote nodes. And then this book provides discussions on on-chip structure and optimizations including the dynamic reconfigurable network， the design of critical path-driven routers and the transmission bypass optimization. They are used to achieve better performance. The third topic focuses on the on-chip memory design， which is called the on-chip networked memory system. The memories are connected by the network with distributed memory management units. At last， the mapping algorithms are discussed， which aim to map the tasks to the on-chip cores with high efficiency and low-power consumption. This book has provided some works innetwork-based manycore systems. The designs and algorithms provided in this book are potential solutions for multicore/manycore architecture. It can be used as the reference for future work and for the researchers who focus on the computer architecture.
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